Reverse-Engineering IBM's G5 Chip

This is the second 90-nm device Chipworks has analyzed that does not use low-k dielectric but instead follows Intel's (Nasdaq: INTC) lead in using strained silicon.

Chipworks, based in Ottawa, analyzes the circuitry and physical composition of semiconductor chips and electronics. Its reports assist engineers in examining different approaches to nanometer silicon.

IBM's Cost and Power Reductions

The new chip allows "significant cost and power reductions," said Julia Elvidge, Chipworks' president, in a statement. "The PowerTune scaling, together with the SOI, allows operation as low as 15 W."

At the IEEE Solid-State Circuits Conference (ISSCC) in February 2004, IBM announced that its 130-nm PowerPC 970 would be shrunk to 90 nm. IBM also reduced die size by almost 50 percent and significantly lowered the chip's power draw.

IBM described the 90-nm process as strained CMOS with silicon-on-insulator (SOI), with a minimum gate length of 46 nm, three gate dielectric thicknesses between 1 and 2 nm and an SRAM cell size of 1.06 microns.

IBM also detailed 10 levels of metal with fluorine-doped TEOS (FTEOS) dielectric, a form of fluoro-silicate glass (FSG), in the back-end process.

The Chipworks Study

Chipworks' analysis confirms a minimum NMOS gate length of 45 nm, and PMOS gate length of 60 nm. The SRAM Tox is 1.5 nm, with a cell size of 1.1 microns.

There are ten layers of copper metallization, with an aluminum bond pad layer and a tungsten local interconnect/contact layer. The SOI body thickness is 45 nm on a 150-nm buried oxide layer.

"Once again IBM has come forward with a leading-edge process, the first to integrate strained silicon and SOI, and impressively small transistors," said Dick James, Chipworks' senior technology analyst.

"Our analysis shows that the NMOS transistors use nitride strain, similar to the Intel Prescott, but there does not appear to be any PMOS strain."

IBM's Newest Research Doesn't Appear

Reports early in the year indicated that IBM might be using a technique they called Strained Silicon Directly on Insulator (SSDOI), in which a Silicon-Germanium (SiGe) layer is used to strain the SOI layer. The SiGe layer is then removed, leaving a strained silicon layer on the buried oxide. This technique strains the NMOS and PMOS transistors simultaneously.

"We have done electron-beam diffraction with our transmission electron microscope (TEM) on the SOI, to look at the crystal structure, but we could not see any lattice distortion. IBM's SSDOI paper indicated that more than 1 percent tensile strain is needed to enhance hole mobility, and we think that this should be visible with TEM analysis," James said in the company statement.

IBM presented the SSDOI work for the first time earlier this year. "It is not surprising that such advanced research has not made it into production yet," James said. "It will be interesting to compare the 970FX with AMD's (NYSE: AMD) 90-nm SOI part, which is currently under analysis in our labs."

Even though IBM's ISSCC paper detailed FTEOS in the back-end, Chipworks was surprised to find FSG as the inter-metal dielectric, since IBM's foundry publicity includes low-k dielectric.

AMAT Equipment

Press reports have rumored that IBM has chosen Applied Materials (Nasdaq: AMAT) ' (AMAT) equipment to develop their own SiCOH low-k film, rather than AMAT's Black Diamond process.

"IBM has been conservative with the 970FX, and used almost the same dielectric stack as in their 130-nm back-end," James said in the statement.

"The dielectric matrix is a bilayer, with an FSG inter-metal layer, with oxide at the via levels, and oxynitride cap layers on the upper metal levels," James said. "There are no etch-stop layers for the metal trenches, but historically IBM have not used them. They have changed the cap layers on the lowest four copper levels to SiOCN to reduce the effective dielectric constant a little."

James continued: "They have been reported to be qualifying low-k during the last few months, and we are expecting to see low-k product soon. We want to compare it with the other low-k processes that we have analyzed."

Comparing AMD, TSMC, Sony, TI and Intel

Chipworks' James presented a detailed review of low-k structures in July. "We looked at three low-k materials, AMAT's Black Diamond, Novellus' Coral and ASM's Aurora, as well as the different implementations by AMD, TSMC, Sony (NYSE: SNE) , TI and Intel," James said.

"We found it fascinating that the detailed structure of each application was different -- good confirmation of the difficulty of integrating these low-k materials. If low-k is not needed for the Apple's performance specifications, it is sensible for IBM to stick with FSG."